A random access memory (RAM) is a particular type of electronic memory wherein each memory address may be directly accessed with a same access time. A binary RAM memory includes an array of memory cells, each one of which is capable of storing a binary information or a bit (that is the logical value “0” or “1”), and corresponding peripheral circuits, which in general accomplish management and access functions for each memory cell.
A static RAM memory cell (SRAM) is a type of volatile RAM memory that does not require any operation for the refresh of the stored data, since the information is stored for a theoretically infinite time (until the shutdown of the electronic system in which such memory is implemented); SRAM memories are often characterized by reduced read times and relatively low power consumption, especially in static conditions.
The reference SRAM memory cell presently used in CMOS technologies includes six transistors, and for this reason it is usually referred to as “6T” memory cell. In particular, a 6T memory cell includes a latch formed by two crossed logic inverters and two access transistors adapted to selectively couple the internal nodes of the latch with a respective pair of bit lines depending on the voltage value of a respective word line. The binary information being stored in the 6T memory cell is given by the voltage values of the internal nodes of the latch. The bit lines are usually brought to a precharge voltage equal to the supply voltage of the memory.
In order to access a 6T memory cell for reading the stored data therein, the voltage of the word line corresponding to the cell is increased to a value corresponding to the supply voltage, so as to enable the two access transistors. In this situation, the bit line connected to the internal node of the latch at the low (ground) voltage value is discharged, while the bit line connected to the internal node of the latch at the high voltage (the supply voltage) stays charged. The voltage difference developing between the two bit lines is then detected by a sense amplifier and converted into a logical value.
The write access to the 6T memory cell is instead performed by bringing one of the two bit lines being associated to the cell down to a low voltage (ground) and then bringing the corresponding word line up to a high voltage (the supply voltage). In this way the internal node of the latch connected to the bit line that has been brought to ground is decreased down to the ground voltage, while the other internal node is increased up to the supply voltage.
However, in a SRAM memory whose cells are of the type just described, it may not be possible to scale the voltage supply by such a quantity to allow a satisfactory reduction in the electric power consumption without incurring in drawbacks that may affect the correct operation thereof.
Such limitation is due to the fact that in a 6T memory cell both the read access and the write access are performed through a same access circuit, being formed by the two access transistors. The fact that such access transistors are used for both reading and writing may make it impractical or impossible to achieve optimal operating conditions in both cases. In fact, during a read operation, it may be desired that the access transistors have a relatively high conduction resistance in order to prevent spurious switchings in the latch and to increase the stability of the cell, while in a write operation it may be desired that such transistors have a sufficiently small conduction resistance to ensure a correct switching of the latch when one of the two bit lines associated with the cell is brought to the ground voltage. In other words, in such a way that both the read noise margins and the write noise margins of a same 6T memory cell turn out to be sufficiently wide, the access transistors of such cell would need to meet conflicting constraints. Such conflicting constraints greatly reduce the tolerance range of the parameters used during the manufacturing process of the SOC system in which a SRAM memory is integrated, thereby bringing down the yield of production. This problem is more evident when the supply voltage of the SOC system, and thus of the SRAM memory, is decreased, since a reduced supply voltage greatly reduces the noise margins.
Reduced noise margins invalidate a correct operation of the memory cell because they do not ensure neither an ideal operation of the latch thereof, nor a good tolerance to spurious switchings caused by alterations in the transfer of electrical signals (for example, voltage glitches).
In addition, a memory cell having reduced noise margins may be affected by so-called indirect access noises. In particular, a noise of such type may occur when the word line of the row wherein there is placed a given memory cell (involved in a read or write operation) is enabled: since each word line is shared by all the memory cells of the corresponding row, enabling a word line implies the selection of cells being not involved in the write or read operation, thereby causing, under unfavorable polarization conditions of the corresponding bit lines, a possible alteration of their logical content (that is, an unwanted write operation).